Two design goals for memory circuits with multiple memory cells are increasing the speed of access to information in the memory circuit and also decreasing the size of the memory circuit. One factor controlling the speed of access to a memory cell is the ratio of the beta of the pull down gate transistor to the beta of the pass gate transistor in the cell. Beta is a characteristic of a transistor that is proportional to the transistor's width divided by its length and relates to the amount of current that can be passed between the source and drain of the transistor. The beta ratio impacts the stability of a memory cell and the speed of access to data stored in from the cell. A high beta ratio is desirable. A high beta ratio means that the pass gate transistor draws a low current in relation to the current of the pull down transistor.
A large beta ratio may be achieved by adjusting the widths of the pass gate and pull down transistors. For example, the width of the pass gate transistor may be decreased to increase the beta ratio. However, as memory cell size approaches the smallest dimensions for a given technology, the minimum transistor width supported by the technology sets the lower limit for the pass gate transistor. Therefore, decreasing the cell size by decreasing the width of the pull down transistor also decreases the beta ratio and thus the stability of the cell.
Heretofore known methods for increasing the beta ratio include increasing the length of the pass gate channel. However, this may have the undesirable effect of increasing word-line capacitance. Another known method for increasing the beta ratio includes either forming a thicker gate oxide or a higher threshold voltage for the pass gate transistor. However, each of these techniques also requires increased processing of the integrated circuit.